The semiconductor industry has continually improved the processing capabilities and power consumption of integrated circuits (ICs) by shrinking a minimum feature size. However, in recent years, process limitations have made it difficult to continue shrinking the minimum feature size for features on the ICs for successive technology nodes. The stacking of two-dimensional (2D) ICs into three-dimensional (3D) ICs has emerged as a potential approach to continue improving processing capabilities and power consumption of ICs.